Japanese Unexamined Patent Publication No. 2004-79602 discloses a nonvolatile memory cell which is configured such that it has, between a control gate and a semiconductor substrate, a nitride film as a charge trap layer which is sandwiched between two oxide films. Electric charge is trapped in the trap layer to thereby cause the cell transistor threshold to vary, and data “0” and data “1” are stored. Since the trap layer is a dielectric layer, the trapped charges are not allowed to migrate within the trap layer. One bit is stored in a first region of the nitride film in close proximity to a first source/drain region which is one of a pair of source/drain regions, and the other bit is stored in a second region of the nitride film in close proximity to a second source/drain region which is the other of the pair of source/drain regions. To sum up, 2-bit information can be stored in the nonvolatile memory cell.
In addition, in some usage cases, only 1-bit information is stored in a nonvolatile memory cell. To this end, the second region of the nitride film is used as a nonuse bit region and is placed in a charge trap state, with data to the nonvolatile memory cell retained, while the first region of the nitride film is used as a use bit region and data is stored depending on the presence or absence of charge in the first region.
The above nonvolatile memory cell is characterized in that, by trapping charge in the nonuse bit region, the time taken to trap (program) charge in the use bit region is shortened, and the retention characteristic of charge trapped in the use bit region, is improved.
On the other hand, Japanese Unexamined Patent Publication No. 2004-110881 discloses a technique in which, in order that the characteristic of a reference cell at the time of reading out data may match the characteristic of a nonvolatile memory cell where the data is stored, the reference cell is arranged in the layout region of the nonvolatile memory cell. The purpose of this is to cause the reference cell to undergo the same history as the history of the bias that is applied to the nonvolatile memory cell, whereby both the cells have the same cell characteristic.
In this case, the characteristic of reference cells may vary due to the variation taking place during fabrication process, the layout position in the nonvolatile memory cell layout region, and so on. In addition, it is also conceivable that the data read-out margin varies depending on, for example, the layout position relationship between a nonvolatile memory cell which is a read-out target and a reference cell. To cope with this, two dynamic reference cells are provided, and DATA “0” is written to one of the two dynamic reference cells, while DATA “1” is written to the other dynamic reference cell. Output currents from the two dynamic reference cells are merged, whereby the read-out margin is secured.
FIG. 13 illustrates by way of example a configuration of each dynamic reference cell having a charge accumulation layer formed by a trap layer, e.g. a nitride film et cetera. Nonvolatile memory cells (16 cells) which are not shown are connected to a common word line. The eight cells on the right hand side together form a block, while the eight cells on the left hand side together form another block. In each block, the nitride film's first and second regions of the nonvolatile memory cells (8 cells) are identified by ADDRESSES (from 8 to f) and by ADDRESSES (from 0 to 7), respectively. With reference to FIG. 13, nitride film's first regions in the blocks that are identified by one of ADDRESSES (from 8 to f) are selected at the same time, and a data parallel read-out operation is performed depending on the presence or absence of charge.
The dynamic reference cell (DRB, DRA) has the same device configuration as the nonvolatile memory cell, and is composed of sixteen cells which are connected to a common word line. In response to addressing to the nonvolatile memory cells, the first regions of the nitride film are identified by ADDRESSES (from 8 to f), while on the other hand the second regions of the nitride film are identified by ADDRESSES (from 0 to 7). The eight cells on the right hand side are a first dynamic reference cell DRB where DATA “01” is stored and the second eight cells on the left hand side are a second dynamic reference cell DRA where DATA “10” is stored.
Here, the notation of DATA “10” and DATA “01” is described. Of the two numeric values arranged side by side, the prefix numeric value is indicative of the presence or absence of charge in the nitride film's first regions of ADDRESSES (from 8 to f) and the postfix numeric value is indicative of the presence or absence of charge in the nitride film's second regions of ADDRESSES (from 0 to 7). The numeric value “1” is indicative of the absence of charge while on the other hand the numeric value “0” is indicative of the injection of charge. DATA “01” which is stored in the first dynamic reference cell DRB is indicative of the state in which charge has been injected to the nitride film's first regions, while no charge exists in the nitride film's second regions, and LOGIC VALUE “0” is stored. On the other hand, DATA “10” which is stored in the second dynamic reference cell DRA is indicative of the state in which no charge exists in the nitride film's first regions, while charge has been injected to the nitride film's second regions, and LOGIC VALUE “1” is stored.
If the nonvolatile memory disclosed in Japanese Unexamined Patent Publication No. 2004-79602 is used in a NAND interface, both the first and second regions of the nitride film of the nonvolatile memory cell must be subjected to an erase operation prior to performing a data program operation.
Generally, a plural number of nonvolatile memory cells are collectively data-erased. In this case, a bias for collective data erase is applied to a memory cell array which is a layout region for the nonvolatile memory cells, so that at the same time the bias is applied also to the dynamic reference cells DRB, DRA arranged in the memory cell array. With reference to FIG. 13, both the nonvolatile memory cells (16 cells) and the dynamic reference cells DRB, DRA (16 cells) are fed an erase operation bias, and they are erased. Such an erase operation places every nonvolatile memory cell and every dynamic reference cell in STATE “11” in which, in the nitride film, neither the first region nor the second region enters the no charged state.
If a nonvolatile memory cell is used as a 1-bit storage cell, charge is preinjected to a nitride film's second region. This operation is called a “preset operation” and is carried out by a program operation to the nitride film's second region. This places every nonvolatile memory cell in STATE “10” in which, in the nitride film, the first region is not charged, but the second region enters the charge injected state.
The above sequence allows the nonvolatile memory cells to enter the programmable state. On the other hand, at this point in time, the dynamic memory cells are held at STATE “11”. Consequently, during the program operation period prior to starting a read-out operation, it becomes necessary to program each dynamic memory cell. With respect to the dynamic reference cell DRA, the second regions of the nitride film corresponding to ADDRESSES (from 0 to 7) are subjected to a program operation so that the dynamic reference cell DRA is placed in DATA “10” STATE. On the other hand, with respect to the dynamic reference cell DRB, the first regions of the nitride film corresponding to ADDRESSES (from 8 to f) are subjected to a program operation so that the dynamic reference cell DRB is placed in DATA “01” STATE. In some memories having a NAND interface, memory cells are programmed while sequentially generating a plural number of addresses within the device in a single program operation. In this case, ADDRESSES (from 8 to f), which are correspond to nitride film's first regions of the nonvolatile memory cells, sequentially vary. A nonvolatile memory cell that is a program target is subjected to a program operation, while simultaneously charge is injected to the first region of each nitride film of the dynamic reference cell DRB. In addition, ADDRESSES (from 0 to 7) sequentially vary, and charge is injected to the second region of each nitride film of the dynamic reference cell DRA. As a result of this, during the program operation period, data programming to the nonvolatile memory cells is carried out and, in addition, the dynamic reference cells DRB, DRA are preset to DATA “01” and to DATA “10”, respectively.